I am running a mobile ESS system based on multiple Victron MultiPlus-II inverters with battery storage. The whole system is controlled by an external software (LabVIEW).
Through a communication table (register IDs), I send the following parameters to each inverter:
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Active power setpoint per unit (e.g. -5000 W per inverter for discharge)
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Permission to charge / discharge
The system is used for different testing and validation purposes.
System setup:
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3-phase connection to building grid via CEE 32 A supply
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External switch logic with contactors
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All inverters switch on after ~60 seconds in a coordinated sequence
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Initial state is pass-through mode (grid is directly passed through)
Control sequence:
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System starts in pass-through mode
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Power setpoints are written (e.g. -5000 W per inverter)
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A signal enables “discharge allowed”
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Expected behaviour: all inverters ramp up to the requested power within seconds
Observed behaviour:
First start (after grid connection):
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System works as expected
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Power setpoints are reached within a few seconds
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Fast and stable response
After grid disconnection and restart:
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Power setpoints are only reached very slowly
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Ramp rate is very low (around ~3 A per minute equivalent)
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In some cases, target power is barely reached or takes a very long time
When this slow ramping happens, the increase is completely constant over time.
It is not stepping or oscillating, but a steady linear ramp until the target value is reached.
It then takes several minutes to reach the requested power setpoint: e.g. 7 minutes for reching 5 kW
Question:
What could cause this very different behaviour between first start and restart after grid loss?
Specifically I would like to understand:
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Does the MultiPlus/ESS system have an internal state after grid loss that limits ramp speed?
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Are there protection or synchronization mechanisms (grid reconnect, DC bus stability, etc.) that reduce power ramp rate?
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Are there known conditions where power ramping is strongly limited (SOC, grid code, frequency/voltage stability, ESS state)?
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Could this also be related to how external control via registers is applied (timing or state transitions)?
Can anyone explain this behaviour and suggest how to fix it?
